HIGH SPEED SIGNALING JITTER MODELING ANALYSIS AND BUDGETING (H/C)

NEW SYSTEM-LEVEL TECHNIQUES FOR OPTIMIZING SIGNAL/POWER INTEGRITY IN HIGH-SPEED INTERFACES--FROM PIONEERING INNOVATORS AT RAMBUS, STANFORD, BERKELEY, AND MIT AS DATA COMMUNICATION RATES ACCELERATE WELL INTO THE MULTI-GIGAHERTZ RANGE, ENSURING SIGNAL INTEGRITY BOTH ON- AND OFF-CHIP HAS BECOME CRUCIAL. SIGNAL INTEGRITY CAN NO LONGER BE ADDRESSED SOLELY THROUGH IMPROVEMENTS IN PACKAGE OR BOARD-LEVEL DESIGN DIVERSE ENGINEERING TEAMS MUST WORK TOGETHER CLOSELY FROM THE EARLIEST DESIGN STAGES TO IDENTIFY THE BEST SYSTEM-LEVEL SOLUTIONS. IN HIGH-SPEED SIGNALING, SEVERAL OF THE FIELD,S MOST RESPECTED PRACTITIONERS AND RESEARCHERS INTRODUCE CUTTING-EDGE MODELING, SIMULATION, AND OPTIMIZATION TECHNIQUES FOR MEETING THIS CHALLENGE. EDITED BY PIONEERING EXPERTS DRS. DAN OH AND CHUCK YUAN, THESE CONTRIBUTORS EXPLAIN WHY NOISE AND JITTER ARE NO LONGER SEPARABLE, DEMONSTRATE HOW TO MODEL THEIR INCREASINGLY COMPLEX INTERACTIONS, AND THOROUGHLY INTRODUCE A NEW SIMULATION METHODOLOGY FOR PREDICTING LIN